Pochio's Relics
A collection of papers and patents written by Chikaaki KODAMA and his colleagues.

Research areas: VLSI CAD, floorplanning and placement algorithms (sequence-pair, Q-sequence etc.)
E-mail: kodama at big.or.jp

Biography:
* Received B.E., M.E. and D.E. degrees in electronic and information engineering from Tokyo University of Agriculture & Technology, Tokyo, Japan, in 1999, 2001 and 2006 respectively.
* My research interests were VLSI layout design, especially floorplanning and packing, and apparel CAD system.
* A member of IEEE and IEICE.

Doctoral thesis: March, 2006, The Studies of Module Placement Representation and Floorplan Extraction for Physical Design of LSI (Advisor, Associate Prof. K. Fujiyoshi).

A reviewer of the following journals and transactions:
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
*Discrete Applied Mathmatics (Elsevire Science)
*Computers & Operations Research (Elsevire Science)
*IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Publications:
Patent | Paper | International Conference | Domestic Conference | Technical Report and etc.
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Patent

1. U.S. Patent Patent: Wiring graphic verification method, program, and apparatus
   Patent No.: US 7,120,881 B2 (US 2005/0005252 A1)
   
   
2. U.S. Patent: Wiring diagram verifying method, program, and apparatus
   Patent No.: US 7,073,142 B2 (US 2004/0143806 A1)
   
   

Paper

1. H. Ohta, T. Yamada, C. Kodama and K. Fujiyoshi,
   ``The O-Sewuence: Representation od 3D-Dissection,''
   IEICE Trans. Fundamentals, vol.E91-A, no.8, pp.2111--2119, Aug., 2008.
   (c) 2008 IEICE
   
2. S. Koda, C. Kodama and K. Fujiyoshi,
   ``Linear Programming-Based Cell Placement with Symmetry Constraints for Analog IC Layout,''
   IEEE Trans. Comput.-Aided Des. Integr Circuits Syst., vol.26, no.4, pp.659--668, Apr., 2007.
   (c) 2007 IEEE
3. K. Fujiyoshi, C. Kodama and A. Ikeda,
   ``A Fast Algorithm for Rectilinear Block Packing Based on Selected Sequence-Pair,''
   Elsevier Science INTEGRATION the VLSI journal, vol.40, issue 3, pp.274--284, Apr., 2007.
   (c) 2006 Elsevier B.V.
   
4. H. Itoga, C. Kodama and K. Fujiyoshi,
   ``A Graph Based Soft Module Handling in Floorplan,''
   IEICE Trans. Fundamentals, vol.E88-A, no.12, pp.3390--3397, Dec., 2005.
   (c) 2005 IEICE (License No. 07RB0050)
   
5. C. Kodama and K. Fujiyoshi,
   ``Minimizing the Number of Empty Rooms by Dissection Line Merge,''
   IEICE Trans. Inf. & Syst., vol.E88-D, no.7, pp.1389--1396, July, 2005.
   (c) 2005 IEICE (License No. 07RB0051)
   
6. K. Wakata, H. Saito, K. Fujiyoshi, K. Sakanushi, T. Obata and C. Kodama,
   ``An Improved Method of Convex Rectilinear Block Packing Based on Sequence-Pair,''
   IEICE Trans. Fundamentals, vol.E86-A, no.12, pp.3148--3157, Dec., 2003.
   (c) 2003 IEICE (License No. 07RB0049)
   
7. C. Kodama and K. Fujiyoshi,
   ``An Efficient Decoding Method of Sequence-pair with Reduced Redundancy,''
   IEICE Trans. Fundamentals, vol.E85-A, no.12, pp.2785--2794, Dec., 2002.
   (c) 2002 IEICE (License No. 07RB0048)
   
   *Papers in Japanese
   
   
8. C. Kodama and K. Fujiyoshi,
   ``Removing Operation of Empty Rooms Based on Sequence-Pair,''
   IEICE Trans. Inf. & Syst. Japanese Edition, vol.J90-D, no.1, pp.1--15, Jan., 2007.
   (c) 2007 IEICE (License No. 07RB0053)
9. S. Koda, K. Fujiyoshi, C. Kodama
   ``On Handling Module Placement with Symmetry Constraints for Analog IC Layout Design,''
   IEICE Trans. Fundamentals Japanese Edition, vol.J89-A, no.6, pp.581--584, June, 2006.
   (c) 2006 IEICE (License No. 07RB0052)
   
10. K. Fujiyoshi, C. Kodama and K. Kiyota,
    ``An Efficient MOVE Operation for Selected Sequence-Pair,''
    IPSJ Journal, vol.46, no.7, pp.1711--1722, July, 2005.
    (c) 2005 IPSJ
    

International Conference (refereed)

1. N. Okada, C. Kodama, T. Sato and K. Fujiyoshi,
   ``Thermal driven module placement using sequence-pair,''
   in IEEE Asia Pacific Conference on Circuits and Systems (APCCAS2006),
   pp.1873--1876, Dec., 2006 (Singapore).
   
   
2. H. Ota, T. Yamada, C. Kodama and K. Fujiyoshi,
   ``The O-Sequence: Representation of 3D-Floorplan dissected by rectangular walls *,''
   in IEEE Ph. D. Research in Microelectronics and Electronics (PRIME2006),
   pp.317--320, Jun., 2006 (Otranto (Lecce), Italy).
   *H. Ota was recieved the honor of GOLD LEAF Certificate.
   (The accepted articles were rated on reviewing scores and top 10% received the GOLD LEAF Certificate.)
   
   
3. Y. Kohira, C. Kodama, K. Fujiyoshi and A. Takahashi,
   ``Evaluation of 3D-Packing representations for scheduling of dynamically reconfigurable systems,''
   in IEEE International Symposium on Circuits and Systems (ISCAS2006),
   pp.4487--4490, May., 2006 (Island of Kos, Greece).
   
   
4. S. Kouda, C. Kodama and K. Fujiyoshi,
   ``Improved method of cell placement with symmetry constraints for analog IC layout design *,''
   in ACM International Symposium on Physical Design (ISPD2006),
   pp.192--199, Apl., 2006 (CA, San Jose).
   *Grant-aided to make a presentation by Foundation for C&C Promotion.
   
   
5. C. Kodama and K. Fujiyoshi,
   ``Removing operation of empty rooms on sequence-pair *,''
   in IEEE Asia Pacific Conference on Circuits and Systems (APCCAS2004),
   pp.521--524, Dec., 2004 (Tainan, Taiwan).
   *Grant-aided to make a presentation by Foundation for C&C Promotion.
   
   
6. C. Kodama and K. Fujiyoshi,
   ``Minimising the number of empty rooms on floorplan by merging dissection lines,''
   in SASIMI2004, pp.402--407, Oct., 2004 (Kanazawa, Japan).
   
   
7. A. Ikeda, C. Kodama and K. Fujiyoshi,
   ``A fast algorithm for rectilinear block packing based on selected sequence-pair,''
   in IEEE Midwest Symposium on Circuits and Systems (MWSCAS2004),
   pp.I-437--I-440, Jul., 2004 (Hiroshima, Japan)
   
   
8. C. Kodama, K. Fujiyoshi and T. Koga,
   ``A novel encoding method into sequence-pair''
   in IEEE International Symposium on Circuits and Systems (ISCAS2004),
   pp.V-329--V-332, May., 2004 (Vancouver, Canada).
   
   
9. C. Kodama and K. Fujiyoshi,
   ``Selected Sequence-Pair: An efficient decodable packing representation in linear time using sequence-pair ,''
   in IEEE Asia South Pacific Design Automation Conference (ASP-DAC2003),
   pp.331--337, Jan., 2003 (Kitakyushu, Japan).
   
   
10. C. Kodama and K. Fujiyoshi,
    ``An efficient decoding method of sequence-pair,''
    in IEEE Asia Pacific Conference on Circuits and Systems (APCCAS2002),
    pp.131--136, Oct., 2002. (Bali, Indonesia -> Singapore)
    
    
11. M. Tsuboi, C. Kodama, K. Sakanushi, K. Fujiyoshi and A. Takahashi,
    ``Linear time decodable rectangular dissection to represent arbitrary packing using Q-sequence,''
    in SASIMI2001, pp.272--278, Oct., 2001 (Nara, Japan).
    
    
12. T. Ohmura, K. Fujiyoshi and C. Kodama,
    ``Area optimization of packing represented by sequence-pair,''
    in IEEE Asia Pacific Conference on Circuits and Systems (APCCAS2000),
    pp.813--816, Dec., 2000 (Tianjin, China).
    
    

Domestic Conference (refereed)

1. S. Kouda, K. Fujiyoshi and C. Kodama,
   "On Handling Module Placement with Symmetry Constraints for Analog IC Layout Design,"
   18th IEICE Circuit and Systems Karuizawa Workshop, pp.229--234, 2005 (in Japanese).
   
   
2. Y. Kohira, C. Kodama, K. Fujiyoshi and A. Takahashi,
   "Evaluation of 3D-Packing for Scheduling of Dynamically Reconfigurable Systems,"
   18th IEICE Circuit and Systems Karuizawa Workshop, pp.211--216, 2005 (in Japanese).
   
   
3. C. Kodama, K. Fujiyoshi and T. Koga,
   "Module Placement Based Floorplan with the Minimal Number of Empty Rooms,"
   17th IEICE Circuit and Systems Karuizawa Workshop, pp.517--522, 2004 (in Japanese).
   
   

Technical Report & Symposium (non refereed)

1. H. Ota, T. Yamada, C. Kodama and K. Fujiyoshi,
   "Floorplan Design for 3D-VLSI,"
   Technical Report IEICE, Vol.VLD2005-75, pp.85--90, Dec., 2005 (in Japanese).
   
   
2. H. Ota, T. Yamada, C. Kodama and K. Fujiyoshi,
   "The O-sequence: Representation of 3D-Floorplan Dissected by Rectangular Walls,"
   IEICE Society Conf., A-1-128(pp.28), 2005 (in Japanese).
   
   
3. N. Okada, C. Kodama, T. Sato and K. Fujiyoshi,
   "Thermal Driven Module Placement Using Sequence-pair,"
   DA Symposium 2005, pp.249--254, Aug., 2005 (in Japanese).
   
   
4. S. Kouda, K. Fujiyoshi and C. Kodama,
   "Improved Method of Module Placement with Symmetric Constraints for Analog IC Layout Design,"
   DA Symposium 2005, pp.243--248, Aug., 2005 (in Japanese).
   
   
5. S. Ono, A. R. Agnihotri, C. Kodama, K. Fujiyoshi and P. H. Madden,
   "Cut Planning and Improved Legalization for Mixed Size Placement,"
   DA Symposium 2005, pp.115--120, Aug., 2005 (in Japanese).
   
   
6. H. Kohira, C. Kodama, K. Fujiyoshi and A. Takahashi,
   "3-D Floorplanning for Scheduling of Dynamically Reconfigurable Systems,"
   Technical Report IEICE, Vol.VLD2004-67, pp.37--42, Nov., 2004 (in Japanese).
   
   
7. A. Ikeda, C. Kodama, A. Nakagomi and K. Fujiyoshi,
   "A Fast Algorithm for Rectilinear Block Packing using SSP,"
   Technical Report IEICE, Vol.VLD2003-103, pp.199--204, Nov., 2003 (in Japanese).
   
   
8. K. Fujiyoshi, C. Kodama and K. Kiyota,
   "An Effective Move Operation for Selected Sequence-Pair,"
   Technical Report IEICE, Vol.VLD2002-6, pp.31--36, May., 2002 (in Japanese).
   
   
9. C. Kodama and K. Fujiyoshi,
   "Selected Sequence-Pair,"
   Technical Report IEICE, VLD2001-17, Vol.101, No.46, pp.65--72, May., 2001 (in Japanese).
   
   
10. C. Kodama, S. Takahashi and K. Fujiyoshi,
    "Automatic Apparel Marking System using Sequence-Pair,"
    Technical Report IPSJ, 2000-MPS, 31-4, pp.9-12, Sep., 2000 (in Japanese).